1. Field of the Invention
The present invention relates to a structure of a capacitive element having a high area efficiency, and in particular to a capacitive element which occupies a small area and is suitable to use in a dynamic semiconductor memory device including memory cells each including one transistor and one capacitor, and also relates to utilization of this capacitance element.
2. Description of the Background Art
Applied products such as personal computers utilizing DRAMs (Dynamic Random Access Memories) have been improved to increase the operation speed and the number of information bits for rapidly processing information. In order to satisfy demands for these applied products, DRAMs used as main memories in the applied products have been improved to increase the operation speed and the number of inputs and outputs (i.e., the number of data I/O bits (the number of I/O nodes)).
Fast operation results in fast charging/discharging of signal lines in the DRAM, and the increase of I/O nodes increases the number of simultaneously operated I/O buffer circuits. Accordingly, a charging current supplied from a power supply line and a discharging current flowing to a ground potential are increased. Therefore, voltage noises on the power supply line and ground line on a DRAM chip increase, and therefore an operation margin, which determines a voltage range for stable operation of internal circuits, decreases, so that stable operation of the DRAM becomes difficult. For example, it is assumed that the device operates stably even with a power supply voltage of 4.5 V when the power supply voltage is 5 V and the voltage noise is 0.5 V. Under the same conditions, when the voltage noise increases to 1.0 V, the circuits operate with the power supply voltage of 4 V due to the voltage noise when the power supply voltage is 5 V, so that it is impossible to ensure a stable operation of internal circuits due to noises when the power supply voltage lowers below 5 V.
In particular, it is a main trend for DRAMS in generations of or after 16 Mbits DRAMs to include internal power supply circuits which produce internal power supply voltages by lowering external power supply voltages. In this internal power supply circuit, an MOS transistor (insulated gate type field effect transistor) is arranged between an external power supply node and an internal power supply line. A gate potential of this MOS transistor is controlled in accordance with a level of a voltage on the internal power supply line, and thereby a quantity of current flowing from the external power supply node to the internal power supply line is controlled for producing the internal power supply voltage at an intended voltage level.
When the internal circuit operates to cause a charging current flowing from the internal power supply line to the internal circuit, the charging current is supplied from the external power supply node through the MOS transistor. The MOS transistor has a channel resistance. Therefore, the channel resistance increases the impedance of the internal power supply line, compared with a structure without the internal power supply circuit. This impedance component further lowers the voltage on the internal power supply line during flow of the charging current (the voltage drop quantity is given by a product of the impedance component Z and the charging current I). Therefore, the voltage noises further increase, resulting in a further remarkable problem of reduction in operation margin.
In order to suppress an influence by the voltage noises on the power supply line and ground line described above, a decoupling capacitance is arranged between the power supply line and the ground line. The decoupling capacitance is arranged near the internal circuit which operates using the power supply voltage on the power supply line and the ground voltage on the ground line as its operation power supply voltages. When the internal circuit operates, it consumes the current supplied from the power supply line, and the power supply voltage on the power supply line lowers. In this case, the decoupling capacitance supplies charges accumulated therein to the internal circuit through the power supply line. This compensates for the current consumed by the internal circuit, and variation in the power supply voltage on the power supply line is suppressed.
Conversely, when the discharging current raises the ground voltage level on the ground line during operation of the internal circuit, the decoupling capacitance absorbs the current discharged from the internal circuit, and thereby suppresses variation in ground voltage on the ground line.
In many cases, semiconductor devices generally use stabilizing capacitances for stably maintaining voltages on predetermined internal nodes as well as charge pump capacitances for generating voltages at predetermined levels. Circuits using the charge pump capacitances include, for example, a charge pump circuit for generating a boosted voltage to be transmitted onto a selected word line, and a charge pump circuit for generating a negative voltage for substrate bias to be applied to a substrate region of a memory cell array in a DRAM.
A current supplied or absorbed by the decoupling capacitance depends on the quantity of charges accumulated therein. Therefore, an effect of suppressing voltage noises by the decoupling capacitance increases as the capacitance value of the decoupling capacitance increases as can be understood from the relationship of Q=C.multidot.V, where Q represents a quantity of accumulated charges, C represents an electrostatic capacity and V represents a voltage applied to the capacitance.
In general, the capacitance value of the capacitance is proportional to an area of opposing portions of electrodes. Therefore, increase in capacitance value of the decoupling capacitance results in increase in occupying area of the capacitance, so that a chip area increases, resulting in increase in chip cost.
In order to achieve sufficient functions of the stabilizing capacitance and charge pump capacitor, the capacitance values thereof must be large. Therefore, similarly to the decoupling capacitance, increase in the capacitance values of these capacitances result in increase in chip cost due to increase in occupied area by such a capacitor.
Japanese Patent Laying-Open No. 64-80066 (1989) discloses a structure for reducing an occupied area by a capacitance without increasing the number of manufacturing steps. In this prior art, a conductive layer formed of the same interconnection layer as an electrode layer of a stacked (i.e., stacked type) capacitor of a memory cell in a DRAM is used to form a capacitor above an MOS transistor. However, the structure disclosed in Japanese Patent Laying-open No. 64-80066 merely utilizes conductive layers of the same interconnection layers as a storage node electrode layer and the cell plate electrode layer of a stacked capacitor as opposing electrodes, and is equivalent to the structure of the capacitor of a parallel plane electrode type. Therefore, it is difficult to achieve a sufficiently large capacitance value with a small occupying area.
Since the insulating film of the capacitance has the same thickness as the insulating film of the memory cell capacitor, the capacitance has a breakdown voltage equal to a half of power supply voltage VCC, so that it is difficult to use the capacitance as the decoupling capacitance for suppressing noises on the power supply line and ground line.
Japanese Patent Laying-Open No. 7-106518 (1995) discloses a structure in which a power supply bypass capacitor, i.e., decoupling capacitance is formed through the same manufacturing steps as those of forming a stacked capacitor of a memory cell in a DRAM. However, the structure disclosed in Japanese Patent Laying-Open No. 7-106518 requires formation of a dielectric film for increasing a breakdown voltage of the decoupling capacitor in the steps of forming the power supply bypass capacitor in addition to the steps of forming of a memory cell capacitor. Therefore, the power supply bypass capacitor cannot be formed with the completely same steps as the stacked capacitor. In the structure disclosed in this Japanese Patent Laying-Open No. 7-106518, the power supply bypass capacitor likewise has a capacitor structure of the parallel plane electrode type, so that it is difficult to achieve a large capacitance value with a small occupied area.